Jagadish Kotra's Homepage

Jagadish B. Kotra Researcher, Tech Lead, Senior Member of Technical Staff (SMTS) @ AMD Research Email: Jagadish.Kotra@amd.com (or) jagadishkotra@gmail.com

About Me

My research appeared in top-tier research venues including: ASPLOS, MICRO, ISCA, SIGMETRICS, FAST, PLDI. I am a (co-)inventor on more than 60 US patents ( Google Patent Profile), received several spotlight/rave and high-five awards, and contributed to several funded proposals at AMD Research. I have successfully transferred some of my research into AMD products. Before joining AMD, I got my PhD from Penn State (in 2017).

Professional Activities

• Technical Program Committee: MICRO (2020, 2021, 2023, 2024), ISCA 2025, ISMM 2024, HPCA 2020 (Industry session), IPDPS 2021, ICCD (2019, 2020), ICPP 2019, IEEE Cluster 2019, MASCOTS 2018
• External Review Committee: HPCA (2019, 2021, 2023) ASPLOS (2019, 2020), ISCA (2020, 2021, 2023), MICRO'22
• Journal Reviewer: TPDS, TCAD, TACO, TC, TODEAS
• Student Research Competition (SRC) Reviewer: CGO'20
• Student Poster/Research Competition (SRC) Chair: CGO'19
• Fundraising Committee: MICRO'19
• Publicity Chair: AIM'17 (Workshop)

Publications

2024

• Xin Wang, Wenjie Xiong, Jagadish B. Kotra, Alex Jones, Xun Jian
  Counter-light Memory Encryption
  In proceedings of IEEE/ACM International Symposium on Computer Architecture
  (ISCA 2024)
  

2023

• Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Vignesh Adhinarayanan, Shaizeen Aga, Derrick Aguren, Varun Agrawal, Ashwin M. Aji, John Alsop, Paul Bauman, Bradford M. Beckmann, Majed Valad Beigi, Sergey Blagodurov, Travis Boraten, Michael Boyer, William Brantley, Noel Chalmers, Shaoming Chen, Kevin Cheng, Michael L. Chu, David Cownie, Nicholas Curtis, Joris Del Pino, Nam Duong, Alexandru Dutu, Yasuko Eckert, Christopher Erb, Chip Freitag, Joseph L. Greathouse, Sudhanva Gurumurthi, Anthony Gutierrez, Khaled Hamidouche, Sachin Hossamani, Wei Huang, Mahzabeen Islam, Nuwan Jayasena, John Kalamatianos, Onur Kayiran, Jagadish B. Kotra, Alan Lee, Daniel Lowell, Niti Madan, Abhinandan Majumdar, Nicholas Malaya, Srilatha Manne, Susumu Mashimo, Damon McDougall, Elliott Mednick, Michael Mishkin, Mark Nutter, Indrani Paul, Matthew Poremba, Brandon Potter, Kishore Punniyamurthy, Sooraj Puthoor, Steven E. Raasch, Karthik Rao, Greg Rodgers, Marko Scrbak, Mohammad Seyedzadeh, John Slice, Vilas Sridharan, Rene van Oostrum, Eric van Tassell, Abhinav Vishnu, Samuel Wasmundt, Mark Wilkening, Noah Wolfe, Mark Wyse, Adithya Yalavarti, Dmitri Yudanov
  A Research Retrospective on AMD’s Exascale Computing Journey
  In proceedings of IEEE/ACM International Symposium on Computer Architecture
  (ISCA 2023, Industry Track)
  

2022

• Xin Wang, Jagadish B. Kotra, Xun Jian
  Eager Memory Cryptography in Caches
  In proceedings of IEEE/ACM International Symposium on Microarchitecture
  (MICRO 2022)
  

• Armin Vakil, Soheil K., Jagadish B. Kotra, Mahmut T. Kandemir
  Athena: An Early-Fetch Architecture To Reduce On-Chip Page Walk Latencies
  International Conference on Parallel Architectures and Compilation Techniques
  (PACT 2022) -- Armin Vakil was mentored by Jagadish Kotra on this project.
  

• Soheil K., Jagadish B. Kotra, Karthik Rao, Mahmut T. Kandemir
  Data Convection: A GPU-Driven Case Study for Thermal-Aware Data Placement in 3D DRAMs
  In proceedings of ACM SIGMETRICS
  (SIGMETRICS 2022) -- Soheil was mentored by Jagadish Kotra on this project.
  

2021

• Jagadish B. Kotra, Michael Lebeane, Mahmut Kandemir, Gabriel H. Loh
  Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources
  In proceedings of IEEE/ACM International Symposium on Microarchitecture
  (MICRO 2021)
  

• Da Zhang, Gagandeep Panwar, Jagadish B. Kotra, Nathan Debardeleben, Sean Blanchard, Xun Jian
  Quantifying Server Memory Frequency Margin and Using it to Improve Performance in HPC Systems
  In proceedings of IEEE/ACM International Symposium on Computer Architecture
  (ISCA 2021)
  

2020

• Jagadish B. Kotra, John Kalamatianos
  Improving the Utilization of Micro-operation Caches in x86 Processors
  In proceedings of IEEE/ACM International Symposium on Microarchitecture
  (MICRO 2020)
  

• Armin Vakil, Mahmut T. Kandemir, Jagadish B. Kotra
  DSM: A Case for Hardware-Assisted Merging of DRAM Rows with Same Content
  In proceedings of ACM SIGMETRICS
  (SIGMETRICS 2020) -- Armin Vakil was mentored by Jagadish Kotra on this project.
  

• Chun-yi Liu, Jagadish B. Kotra, Myoungsoo Jung, Mahmut T. Kandemir
  Centaur: A Novel Architecture for Reliable, Low-Wear, High-Density 3D NAND Storage
  In proceedings of ACM SIGMETRICS
  (SIGMETRICS 2020)
  

• Vamsee Reddy K., Jagadish B. Kotra, Clayton Hughes, Hammond S. David, Amro Awad
  PreFAM: Understanding the Impact of Prefetching in Fabric-Attached Memory Architectures
  In proceedings of International Symposium on Memory Systems
  (MEMSYS 2020)

• S.R. Swamy, Sumitha George, Hariram Govindarajan, Jagadish B. Kotra, Madhu Mutyam, Jack Sampson, Mahmut T. Kandemir, Vijaykrishnan Narayanan
  Optimization of Inter-Cache Traffic Entanglement in Tagless Caches with Tiling Opportunities
  In proceedings of CASES
  (CASES 2020)
  

2019

• Anup Sarma, Huaipan Jiang, Ashutosh Pattnaik, Jagadish B. Kotra, Mahmut T. Kandemir, Chita R. Das
  CASH: Improving DRAM Energy Efficiency in CPU-based Inference
  In proceedings of The International Symposium on Memory Systems
  (MEMSYS 2019)
  

• Chun-yi Liu, Jagadish B. Kotra, Myoungsoo Jung, Mahmut T. Kandemir, Chita R. Das
  SOML Read: Rethinking the read operation granularity of 3D NAND SSDs
  In proceedings of The 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems
  (ASPLOS 2019)
  

2018

• Jagadish B. Kotra, Haibo Zhang, Alaa R. Alameldeen, Chris Wilkerson, Mahmut Kandemir
  CHAMELEON: A Dynamically Reconfigurable Heterogeneous Memory System.
  In proceedings of 51st Annual IEEE/ACM International Symposium on Microarchitecture
  (MICRO 2018)
  

• Sumitha George, Minli Julie Liao, Huaipan Jiang, Jagadish B. Kotra, Mahmut Kandemir, Jack Sampson, Vijaykrishnan Narayanan
  MDACache:Caching for Multi-Dimensional-Access Memories.
  In proceedings of 51st Annual IEEE/ACM International Symposium on Microarchitecture
  (MICRO 2018)
  

• Orhan Kislal, Jagadish B. Kotra, Xulong Tang, Mahmut T. Kandemir, Myoungsoo Jung
  Enhancing Computation-to-Core Assignment with Physical Location Information.
  In proceedings of Programming Language Design and Implementation
  (PLDI 2018)
  

• Chun-yi Liu, Jagadish B. Kotra, Myoungsoo Jung, Mahmut T. Kandemir
  PEN: A Design of Partial-Erase for 3D NAND-based High Capacity SSDs
  In proceedings of 16th USENIX Conference on File and Storage Technologies
  (FAST 2018)
  

• Huaipan Jiang, Anup Sarma, Jihyun Ryoo, Jagadish B. Kotra, Meenakshi Arunachalam, Chita R. Das, Mahmut T. Kandemir
  A Learning-guided Hierarchical Approach for Biomedical Image Segmentation.
  In proceedings of 31st IEEE International System-On-Chip Conference
  (SOCC 2018)
  

2017

• Jagadish B. Kotra
  Hardware-Software Co-Design for Optimizing Memory Hierarchy In Many-Core and Multi-Socket Systems.
  Ph.D. Dissertation
  

• Jagadish B. Kotra, Narges Shahidi, Zeshan A. Chisthi, Mahmut T. Kandemir
  Hardware-software co-design to mitigate DRAM refresh overheads.
  In proceedings of The 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems
  (ASPLOS 2017)
  

• Jagadish B. Kotra, Seongbeom Kim, Kamesh Madduri, Mahmut T. Kandemir
  Congestion-Aware Memory Management on NUMA Platforms: A VMware ESXi case study.
  In proceedings of 2017 IEEE International Symposium on Workload Characterization
  (IISWC 2017)
  

• Jagadish B. Kotra, Diana Guttman, Nachiappan Chidambaram, Mahmut T. Kandemir, Chita R. Das
  Quantifying the potential benefits of on-chip near-data computing in manycore processors.
  In proceedings of The IEEE 25th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
  (MASCOTS 2017)
  

• Orhan Kislal, Jagadish B. Kotra, Xulong Tang, Mahmut T. Kandemir, Myoungsoo Jung
  Location-Aware Computation Mapping for Manycore Processors.
  In proceedings of The 26th International Conference on Parallel Architectures and Compilation Techniques
  (PACT 2017 - Poster)
  

2016

• Xulong Tang, Mahmut T. Kandemir, Praveen Yedlapalli, Jagadish B. Kotra
  Improving Bank-Level Parallelism for Irregular Applications.
  In proceedings of The 49th Annual IEEE/ACM International Symposium on Microarchitecture
  (MICRO 2016 - Best Paper Nominee)
  

• Jagadish B. Kotra, Mohammad Arjomand, Diana Guttman, Mahmut T. Kandemir, Chita R. Das
  Re-NUCA: A Practical NUCA Architecture for ReRAM based last-level caches.
  In proceedings of The International Parallel and Distributed Processing Symposium
  (IPDPS 2016)
  

• Orhan Kislal, Mahmut T. Kandemir, Jagadish B. Kotra
  Cache-Aware Approximate Computing for Decision Tree Learning
  In proceedings of The International Parallel and Distributed Processing Symposium
  (IPDPS Parlearning Workshop 2016)
  

2015

• Jun Liu, Jagadish B. Kotra, Wei Ding, Mahmut T. Kandemir
  Network footprint reduction through data access and computation placement in NoC-based manycores.
  In proceedings of The 52nd Annual Design Automation Conference
  (DAC 2015)
  

• Joshua Dennis Booth, Jagadish B. Kotra, Hui Zhao, Mahmut T. Kandemir, Padma Raghavan
  Phase Detection with Hidden Markov Models for DVFS on Many-Core Processors.
  In proceedings of The 35th International Conference on Distributed Computing Systems
  (ICDCS 2015)
  

• Karthik Swaminathan, Jagadish B. Kotra, Huichu Liu, Jack Sampson, Mahmut T. Kandemir, Vijaykrishnan Narayanan
  Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures.
  In proceedings of The 28th International Conference on VLSI Design
  (VLSID 2015)
  

2013

• Praveen Yedlapalli, Jagadish B. Kotra, Emre Kultursay, Mahmut T. Kandemir, Chita R. Das, Anand Sivasubramaniam
  Meeting midway: Improving CMP performance with memory-side prefetching.
  In proceedings of The 22nd International Parallel Architectures and Compilation Techniques.
  (PACT 2013)
  

Patents

Internship Experience

• Internship at Intel Labs, Spring 2016
  

• Internship at VMware Inc., Summer 2015
  

• Internship at Intel Corp., Summer 2013
  

Job Experience

• Senior Member Of Technical Staff, AMD Research, Austin, Texas. [Current role]
  

• Member Of Technical Staff, AMD Research, Austin, Texas.
  

• Post-doctoral Researcher, AMD Research, Austin, Texas.
  

• Hardware-Software Co-design Engineer, IBM Labs, India. [ August 2006 - July 2010 ]
  

Educational Background

• PhD in Computer Science and Engineering, The Pennsylvania State University

  August 2010 - August 2017

• B.Tech in Electronics and Communications Engineering, Acharya Nagarjuna University

  August 2002 - July 2006

Personal Hobbies: I am an avid squash/badminton/raquetball player and share general enthusiasm for all kinds of sports.